J-k master-slave flip-flop

ABSTRACT

Disclosed is a J-K master-slave flip-flop system having a simplified gating system and in which no clock pulse connections are required for the transfer transistors. Clock pulses are fed to input gates. Additional clocks may be added by tying the input gates to clock lines. The clock pulse are ANDed together at the input gate so that the J-K master-slave flip-flop system is suitable for use in large arrays.

United States Patent {72] Inventor Jeflrey C. Kalb San Jose, Calif. 21Appl. No. 681,281 [22] Filed Nov. 7, 1967 [45] Patented July 6, 1971[73] Assignee Texas Instruments Incorporated Dallas, Tex.

[54] .l-K MASTER-SLAVE FLIP-FLOP 9 Claims, 5 Drawing Figs.

[52] US. Cl 307/247, 307/215, 307/269, 307/291 [5 I] lnt.Cl H03k 17/00[50] Field of Search... 307/247, 269, 215

[56] References Cited UNITED STATES PATENTS RE26,082 9/1966 Osborne307/215 7/1965 Monahan 307/247 3,229,119 1/1966 Bohn 307/215 3,247,3994/1966 Moody 307/269 3,430,070 2/1969 Marshall 307/247 PrimaryExaminerDonald D. Forrer Assistant Examiner-Harold A. DixonAtr0rneysSamuel M. Mims, Jr., James 0. Dixon, Andrew M. Hassell, HaroldLevine, Melvin Sharp, John E. Vandigriff and James C. Fails ABSTRACT:Disclosed is a J-K master-slave flip-flop system having a simplifiedgating system and in which no clock pulse connections are required forthe transfer transistors. Clock pulses are fed to input gates.Additional clocks may be added by tying the input gates to clock lines.The clock pulse are ANDed together at the input gate so that the J-Kmaster-slave flip-flop system is suitable for use in large arrays.

' OUTPUT TRANSISTOR CLOCK PATENIED JUL 6 I97! SHEET 1' OF 3 JEFFREYCLIFFORD KALB IN VENTOR ATTORNEY LOAD .I-K MASTER-SLAVE FLIP-FLOP Thepresent invention relates to electrical flip-flop circuits and moreparticularly to J-K master-slave flip-flop circuits.

An object of the invention is to provide a J-K master-slave flip-flopwith a minimum load upon the clock.

Another object of the invention is to provide a J-K masterslaveflip-flop which is entirely free of internal race conditions.

Other objects, features and advantages of the invention will be bestunderstood by reference to the following detailed description when readin conjunction with the appended claims and attached drawings in whichlike reference symbols indicate like parts and in which: 1

FIG. 1 illustrates a block diagram of a J-K master-slave flipflopaccording to the present invention;

FIG. 2 illustrates embodiment of a J-K master-slave flipflop accordingto the invention;

FIG. 3 illustrates a 'I'TL NAND gate used in the embodiment of FIG. 2;

FIG. 4 illustrates a timing diagram of the operation of the embodimentof FIG. 2; and

FIG. 5 illustrates a timing diagram of the operation of the embodimentof FIG. 2; and

FIG. 5 illustrates the input-output transfer characteristics of the TTLNAND input-gates of the embodiment of FIG. 2.

Referring to FIG. I, a block diagram of a J-K master-slave flip-flopaccording to the present invention is illustrated and indicated byreference No. 9. Input information is received through the J,-K, inputsto the input gages I1 and 12. A clock pulse from the clock 13 and anoutput feedback from each of the output circuits [6 and 17 are alsoreceived at the two input gates II and 12. Information is entered fromthe J,K, inputs to the master flip-flop I0 when the clock pulse goeshigh, that is when the positive edge of the clock pulse occurs. Theinformation stored in the master flip-flop 10 is then transferredthrough the transfer gates 14 and 14A to the slave flip-flop 15 when theclock pulse goes low, that is, when the negative edge of the clock pulseoccurs. The state of the slave flip-flop ap pears at the outputs Q andGas binaryhigh-low voltage level outputs from the output circuits 16 and17.

The clear and preset controls (shown in FIG. 2) allow the J K masterslave flip-flops I0 and 15 to be set to either state, Q=l and 0 5, or 00 and 6 1. The input-output logic table for the J-K master slaveflip-flop 9 is shown in Table I below:

1 Compliments initial output.

It is to be noted that in the logic shown in Table l, the logic state Iis to be represented by a high voltage and the logic state 0 is to berepresented by a low voltage.

Referring to FIG. 2, a JK master slave flip-flop designed according tothe present invention is illustrated. The master slave flip-flop iscomprised of six TTL NAND gates, G,G two transfer transistors T, and Tsix output transistors T T,,, sixteen resistors R,R,,,, one referencediode D, and two biasing voltages Vcc, and Vcc, The gates G, and G andresistors R,R, comprise the two input gates for the master slaveflip-flop. The gates G and G and resistors R and R comprise the masterflip-flop which is set in accordance with the .l-K inputs to gates G,and G when the positive edge of the clock pulse occurs. Gates G,G, areconnected to ground through the reference diode D. Transistors T, and Tcomprise the transfer gates 14 and 14A of FIG. 1 respectively. They arethe means of information transfer between the master flip-flop l0 andthe slave flip-flop 15. T, and T isolate the master flipflop 10 from theslave flip-flop 15 while the master flip-flop I0 is being set at thepositive edge of a clock pulse and transfers the information from themaster flip-flop 10 to the slave flipflop 15 at the negative edge oftheclock pulse.

Gates G and G, and resistors R-,R,,, comprise the slave flip-flop 15which is set in accordance with the information received from the masterflip-flop through transistors T, and T at the negative edge of the clockpulse. Transistors T -T,, and resistors R,,R,,, comprise outputcircuitry 16 and 17 which provides the J-K master slave flip-flop withlow output impedance, low noise pickup and good capacitive drivecharacEristics. The binary output of the master slave flip-flop, O andQ, is taken from the output circuitry.

Referring to FIG. 3, each of the six TTL NAND gates shown in FIG. 2comprises two NPN transistors T, and T and biasing resistors R and R,,.T, is a multiple emitter transistor and its several emitters comprisethe inputs to the NAND gate. The base of T, is connected to the biasingvoltage V through R,, and the collector is connected to the base of theoutput transistor T,,. The collector of T, is connected to the biasingvoltage V through R, and its emitter is connected to ground through thediode D' (gates G,G,) or through a passive resistance (gates G and G Thevoltage states of the T, input emitters determine whether T, will be inthe On or Off state as the current of transistors T, flows eitherthrough the base-collector P-N junction thereof or through one of thebase-emitter P-N junctions. If the inputs to all emitters of T, are inthe high state, the base-emitter P-N junctions will all be reversebiased and cur rent will flow through the basecollector junction to thebase of T turning T On. If one or more of the emitter inputs of T, arelow, the respective base-emitter P-N junctions of such emitters will beforward biased and the current of transistor T, will be diverted fromthe collector to such emitters. In this state no drive current reachesthe base of T and T, is turned Off.

The input threshold voltage for a high input is determined by thevoltage across the external circuitry Load plus the baseemitter voltageV of output transistor T Any input emitter voltage to T, below thislevel will forward bias the base-emitter junction of the emitter towhich it is applied. When all T, emitters are high, the drive current totransistor T is sufficient to saturate it, causing its collector voltageto go low. When no drive current reaches T T is Off and the collector isat the high voltage impressed upon it by V The output of the NAND gateis the voltage of the T, collector. It is to be noted that for the TTLNAND gate illustrated, the logical state 1 is represented by a highvoltage and the logical state 0 is represented by a low voltage.

Transistors T, through T,, (in FIG. 2) are NPN transistors with suitablesaturation characteristics for digital circuitry use. Diode D is aP-Njunction semiconductor diode.

The functional relationships between the components of the master-slaveflip-flop may be best understood by reference to the operation of theflip-flop in response to a sample set of inputs while in a given initialoutput state. For purposes of this description, the assumed initialoutput state is Q in the logical 1 state and Gin the logical 0 state.The sample inputs are J, through l in the logical 1 state, K, through Kin the logical I state, clear in the logical I state and preset in thelogical 1 state. As seen from Table 1 above, after the clock pulseoccurs, the output state will be Q in the 0 state and O in the 1 state,the complementof the initial output state. As will become evidentsubsequently, for Q to be initially in the logical 1 state, that is at ahigh voltage, transistor T, must be On, transistor T must be Off, gate Gmust have a logical 1 output and gate G, must have a logical 0 output.

The timing diagram for the operation of the master-slave flip-flop underthe conditions stated above is illustrated in FIG. 4 and will bereferred to during the description of the flip-flop operation.

At time t, of FIG. 4, the .l and K inputs and the positive edge of theclock pulse are all present at the input gates of the master-slaveflip-flop. Referring to H6. 2. gate G, has a low voltage logical inputfrom O. regardless of the clock and J in puts, forcing its output to thelogical 1 state. It is thus disabled by O and its logical output at thecollector of transistor T does not change. Gate G,, however, has allinputs in the logical l or high state. The basecollectorjunction oftransistor T,- is thus forward biased and base current is fed totransistor T Transistor T begins to turn On in response to the basecurrent it is now receiving. As transistor T, turns On, the outputvoltage at its collector begins to drop. When the voltage becomessufficiently low, the emitter of transistor T which is connected to thecollector of transistor T will begin to draw the transistor current of Tand transistor T,,, will be turned Off. As T,,, turns Off, its collectorvoltage rises. This voltage is connected to one of the emitter inputs oftransistor T The other two emitter inputs of T, are connected to thecollector of transistor T and preset. Since these two inputs are in thelogical l or high state, as T turns Off, all inputs to T reach the highstate and T is turned On. Gate G now has a logical O or low output andgate G, has a logical l or high output. The master flip-flop has beenset in accordance with the 1-K inputs.

Transistors T, and T effectively isolate the master flip-flop from theslave flip-flop during this setting of the master flipflop. As notedabove, T, was On prior to the occurrence of the positive edge of theclock pulse. As T turns Off, however, the emitter of T, which isconnected to the collector of T goes high and the base emitter junctionof T, is reverse biased and T, turns Off, causing its collector to gohigh. This has no effect on the slave flip-flop since gate G, receivesboth the Q voltage and the T, collector voltage at its input emitters.Since 6 remains low, the change in state of T, does not affect the gate6,.

Before the clock pulse, transistor T was Off and effectively opencircuited at its emitter by transistor T which was then Off. Although Tturned On when the positive edge of the clock pulse occurs, T remainsOff. For T to turn On, its base voltage would have to reach the voltageV plus Vwmmm" 2 above the voltage of the reference diode D, where V,,the base-emitter forward diode voltage of T and where Vmmmm the basevoltage required for T to operate in the saturated region. However, thevoltage to the base of T is the output voltage of the collector of T,,,.This voltage has dropped low enough to turn transistor T,, On.Therefore, it must have gone below the Voltage hf omit! 4 above therelerence diode D. where m4 the base emitter junction voltage oftransistor T,,, and where V the difference between the base-emitterforward diode voltage and the base-collector forward diode voltage of Tabove the reference diode D. So long as V Vwmmm 2 is equal to or greaterthan V V the base voltage into transistor T will have fallen below thatrequired to turn On T before T is turned On. The low emitter voltage Treceives as T turns On has no effect upon it and T remains Off,preventing the setting of the master flip-flop from affecting the slaveflip-flop. The difference in the two voltages V Vmmm" 2 and V V insuresthe isolation of the master and slave flip-flops. The J-K master slaveflip-flop 9 is free of any internal race" conditions as the transfertransistors eliminate the possibility of signals being transferredbetween the master and slave flip-flops at improper times. Even if thetwo voltages are the same, propagation delay through gates G, and G,required before the emitter of of transistor T goes low will preventinternal race. The same relationship that exists between transistors T Tand T also exist between transistors T,, T and T,, to prevent internalrace when the JK inputs are such as to set the master flip-flop in theopposite sense to that described, causing the emitter of T, to go low.The collector of T will be below V l-v (V base-emitter forward diodevoltage ofT, and V ,=the base voltage required for T, to operate in thesaturated region) and T, will not be able to turn On.

The master flip-flop now contains the new information entered while theslave flip-flop contains the information entered previously. Thetransistors T, and T isolate the two flip-flops.

At any time after the master flip-flop is set, the negative edge of aclock pulse may occur. ln circuits built and tested, the time requiredfor setting the master flip-flop has been as small as 7 nanoseconds.When the negative edge of the clock pulse occurs, gate G, remainsunaffected due to the inhibiting effect ofO being low. However, with theclock now going low, the respective input emitter of T to the base oftransistor T, ceases, turning Off T As T, turns Off, the output voltageat its collector rises. As the collector voltage rises, it reaches VV,,,,,,.,,,,,,,, the base voltage required for T to turn On and T turnsOn. The input emitter to transistor T, connected to the collector oftransistor T is now connected to ground through T T and the referencediode D. The input threshold for a high input to gate G is set by theoutput transistor T and resistors R, and R to be above the voltageacross T T and reference diode D. The voltage to the emitter of T isthus sufficiently low to forward bias the respective base-emitterjunction and the driving current from T to T ceases and transistor Tturns Off. This turns Off transistor T and turns On T and T,. The outputbiasing voltage V now drives transistors T and T, with the result that Ois high. At the same time, T is now Off and T, is essentially opencircuited. The Q, T, and preset inputs to gate G are now all high, withthe result that T is turned On and the collector voltage of T goes low.Transistor T,, is thus turned On and turns Off transistors T and T withthe result that Q goes low. The transfer of information from the masterflip-flop to the slave flip-flop and output circuits has beenaccomplished and the outputs now are Q low or 0 and Ohigh or 1, asrequired by the logic of the j-K master slave flip-flop as given inTable I.

It can now be seen that when 0 was in the initial high state, gate G,,must have been receiving a low input from T,, and gate G must have beenreceiving a high input from T that is, T, was On and T was Off. For T,to be On, the output of gate G, had to be low, and for T to be Off, theoutput of gate 0,, had to be high. This is thejustification for theassumption of T, On, T Off, and 0;, high, G, low, as the initial stateof the flip flop in the above description.

The operation of the J-K master slave flip-flop in response to the otherpossible combinations of input signals and to the clear and presetsignals is similar to that described above. It is to be noted that ifQis to be initial 1y low, gate G is disabled and gate G, is enabled,whereas if Q is initially low, gate G, is disabled and gate 0, isenabled. No change of output state will occur unless an enabled inputgate receives all logical 1 inputs. Special reference is made to theclear and preset signals. The preset signal is received at gates G G andG5 and results in setting the master and slave flip-flops simultaneouslyso that Q is set to the logical 1 state and 6 is set to the logical 0state. The clear signal is received at gates G,, G, and G and results inthe simultaneous setting of the master and slave flip-flops so that Q isset to the logical 0 state andO is set to the logical 1 state. Thepresent and clear signals are normally in the high or logical 1 state,so as not to affect the action of the gates. To cause preset or clear tooccur, the respective signal is made to go low, causing a base-emitterforward biasing to occur at each of the multiple emitter transistors towhich it is applied and forcing a high output for that gate.

lnterconnecting the transfer transistors T, and T with the input gates,G, and G the master flip-flop gates G,, and G, and the slave flip-flopgates G and G in the configuration illustrated in FIG. 2 provides manyadvantages for the .l-K master slave flip-flop.

The .lK masterslave flip-flop requires no clock pulse connections to thetransfer transistors. The clock pulse line is connected only to theinput gates G, and G This makes for a minimum power load upon the clock,a definite advantage in large arrays of flip-flops. With the clock beingfed only to the input gates, more clocks can be added by simply tyingthe input emitter leads of the input gates to the clock lines. The

clock pulses will then be ANDed at the input gates. This is especiallydesirable where the .l-K master-slave flip-flop is embodied in anintegrated circuit and additional connections to the transfer gatescannot be made after fabrication.

The transfer transistors T and T connected in the configuration shownalso provide the isolation between the master flip-fiop and the slaveflip-flop during the time that the master flip-flop I0 is being set anduntil the negative edge of the clock pulse occurs. The configuration.uses the inherent junction voltages of the transistors in the gates G,Gand the junction voltages and saturation voltages of the transfertransistors T and T to obtain total elimination of internal raceconditions with a minimum of circuit components.

Because of this complete elimination of internal race conditions and theANDing of the input signals at the input gates G, and 0,, the J-Kmaster-slave flip-flop according to the present invention is especiallysuitable for use in large arrays where several clock lines may berequired to supply clock pulses to many J-K master slave flip-flops. Dueto propagation delays and other inequalities in clock lines and clockflip-flops, clock skew, a slight time staggering of the clock pulses,occurs. The J-K master slave flip-flop according to the presentinvention is relatively insensitive to such clock skew. So long as oneinput to both gates is low, no change in state of the master slaveflipflop may occur. Thus, if the J-K inputs arrive at the input gatesbefore the clock pulse arrives, no change in state occurs until theclock pulse arrives.

During the times when the clock pulse is low, the J-K inputs may changestates and have no effect upon the J-K master slave flip-flop 10. Theonly requirement for proper operation of the flip-flop 10 is that duringthe time when the clock pulse is high, the 1-K inputs remain constant.Since the clock pulse can be as narrow as 7 nanoseconds, this is a verylow requirement of stability.

The reference diode D allows the input voltage threshold to the J-Kmaster slave flip-flop to be set within a wide range of desired D-Clevels. The threshold voltage for a high or logical 1 input isdetermined by the diode voltage of the reference diode D, plus the Vvoltages of transistors T T T and T T or T will be at the voltage levelV rV of T or T,,. For a logical l or high input to occur, the inputvoltage must be above this voltage in order the base-collector diode ofT or T to be forward biased. The reference diode D allows a high D-Cthreshold at the input to be maintained with a minimum of circuitcomponents and as shown in FIG. 5, provides gates G,G with a rectilineartransfer characteristic desirable in array applications.

it is to be understood that the above-described embodiments are merelyillustrative of the invention. Other arrangements may be devised bythose skilled in the art without departing from the spirit and scope ofthe invention.

lclaim:

l. A master-slave flip-flop comprising in combination:

a. first and second multiple input gate circuits, each including atleast one multiple emitter transistor, said first and second gatecircuits being interconnected to form a master flip-flop having twooutput states;

b. third and fourth multiple input gate circuits, each including atleast one multiple emitter transistor, said third and fourth gatecircuits being interconnected to form a slave flip-flop having twooutput states;

c. first circuit means for interconnecting said master and said slaveflip-flops; and

d. second and third circuit means for respectively applying plural inputsignals and at least one clock signal to said first and second multipleinput gate circuits, said input and clock signals having at least twoconditions;

e. said master flip-flop includes means responsive to one condition ofsaid input signals and one condition of said clock signal for changingthe state of said master flip-flop, and said slave flip-flop includesmeans responsive to said master flip-flop and the other condition ofsaid clock signal for changing the state of said slave flip-flop aftersaid master flip-flop changes state.

2. A master-slave flip-flop in accordance with claim 1 wherein 'saidfirst circuit means includes two transistors for respectively couplingthe outputs ofsaid master flip-flop to the inputs of said slaveflip-flop.

3. A master-slave flip-flop in accordance with claim 1, wherein each ofsaid second and third circuit means includes at least one multipleemitter transistor.

4. A master-slave flip-flop in accordance with claim 1 and furtherincluding fourth circuit means for applying clear and preset signals tosaid master and said slave flip-flops, whereby the states of said masterand slave flip-flops are selectively changed in response to said clearand present signals.

5. A master-slave flip-flop in accordance with claim 1 wherein saidfirst, second, third and fourth multiple input gate circuits areinverting gate circuits.

6. A master-slave flip-flop in accordance with claim 5 wherein said JKsignals and clock signals are selectively coupled to said masterflip-flop by fifth and sixth NAND gates, with each of said NAND gateshaving at least one multiple emitter transistor.

7. A master slave flip-flop comprising in combination:

a. a master flip-flop comprising first and second interconnected NANDgates with each of said NAND gates having at least one multiple emittertransistor, said master flip-flop having two output states;

b. a slave flip-flop comprising third and fourth interconnected NANDgates, with each of said NAND gates having at least one multiple emittertransistor, said slave flipflop having two output states;

c. circuit means for interconnecting said master and said slaveflip-flops, said circuit means being responsive to J-K signals and clocksignals, with each of said signals having at least a high and a lowlevel d. the output state of said master flip-flop includes meansresponsive to one of said 1-K signals and the high level of said clocksignal for changing the state of said master flipflop, and said slaveflip-flop includes means responsive to said master flip-flop and the lowlevel of said clock signal for changing the state of said slaveflip-flop after said master flip-flop changes state.

8. A master-slave flip-flop in accordance with claim 7 wherein saidcircuit means include first and second transistors for respectivelycoupling the outputs of said master flip-flop to the inputs of saidslave flip-flop.

9. A master-slave flip-flop system comprising in combinatron:

a. a master flip-flop circuit having cross-coupled multiple emittertransistors, said master flip-flop having two output states;

b. a slave flip-flop circuit having cross-coupled multiple emittertransistors, said slave flip-flop circuit having two output states;

c. first and second transfer gate circuits respectively coupled betweenthe output of said master flip-flop and the input of said slaveflip-flop; and

d. first and second multiple input gate circuits for respectivelyapplying plural input signals and at least one clock signal to the inputof said master flip-flop, each of said input gate circuits including atleast one multiple emitter transistor and said input and clock signalshave at least two conditions; wherein e. said input signals areselectively applied to said first and second multiple input gatecircuits and said clock signal is applied to said master flip-flop; and

. said master flip-flop includes means responsive to one condition ofsaid input signals and one condition of said clock signal for changingthe state of said master flip-flop, and said slave flip-flop includesmeans responsive to said master flip-flop and the other condition ofsaid clock signal for changing the state of said slave flip-flop aftersaid master flip-flop changes state.

1. A master-slave flip-flop comprising in combination: a. first andsecond multiple input gate circuits, each including at least onemultiple emitter transistor, said first and second gate circuits beinginterconnected to form a master flip-flop having two output states; b.third and fourth multiple input gate circuits, each including at leastone multiple emitter transistor, said third and fourth gate circuitsbeing interconnected to form a slave flip-flop having two output states;c. first circuit means for interconnecting said master and said slaveflip-flops; and d. second and third circuit means for respectivelyapplying plural input signals and at least one clock signal to saidfirst and second multiple input gate circuits, said input and clocksignals having at least two conditions; e. said master flip-flopincludes means responsive to one condition of said input signals and onecondition of said clock signal for changing the state of said masterflip-flop, and said slave flip-flop includes means responsive to saidmaster flip-flop and the other condition of said clock signal forchanging the state of said slave flip-flop after said master flip-flopchanges state.
 2. A master-slave flip-flop in accordance with claim 1wherein said first circuit means includes two transistors forrespectively coupling the outputs of said master flip-flop to the inputsof said slave flip-flop.
 3. A master-slave flip-flop in accordance withclaim 1, wherein each of said second and third circuit means includes atleast one multiple emitter transistor.
 4. A master-slave flip-flop inaccordance with claim 1 and further including fourth circuit means forapplying clear and preset signals to said master and said slaveflip-flops, whereby the states of said master and slave flip-flops areselectively changed in response to said clear and present signals.
 5. Amaster-slave flip-flop in accordance with claim 1 wherein said first,second, third and fourth multiple input gate circuits are inverting gatecircuits.
 6. A master-slave flip-flop in accordance with claim 5 whereinsaid J-K signals and clock signals are selectively coupled to saidmaster flip-flop by fifth and sixth NAND gates, with each of said NANDgates having at least one multiple emitter transistor.
 7. A master slaveflip-flop comprising in combination: a. a master flip-flop comprisingfirst and second interconnected NAND gates with each of said NAND gateshaving at least one multiple emitter transistor, said master flip-flophaving two output states; b. a slave flip-flop comprising third andfourth interconnected NAND gates, with each of said NAND gates having atleast one multiple emitter transistor, said slave flip-flop having twooutput states; c. circuit means for interconnecting said master and saidslave flip-flops, said circuit means being responsive to J-K signals andclock signals, with each of said signals having at least a high and alow level d. the output state of said master flip-flop includes meansresponsive to one of said J-K signals and the high level of said clocksignal for changing the state of said master flip-flop, and said slaveflip-flop includes means responsive to said master flip-flop and the lowlevel of said clock signal for changing the state of said slaveflip-flop after said master flip-flop changes state.
 8. A master-slaveflip-flop in accordance with claim 7 wherein said circuit means includefirst and second transistors for respectively coupling the outputs ofsaid master flip-flop to the inputs of said slave flip-flop.
 9. Amaster-slave flip-flop system comprising in combination: a. a masterflip-flop circuit having cross-coupled multiple emitter transistors,said master flip-flop having two output states; b. a slave flip-flopcircuit having cross-coupled multiple emitter transistors, said slaveflip-flop circuit having two output states; c. first and second transfergate circuits respectiVely coupled between the output of said masterflip-flop and the input of said slave flip-flop; and d. first and secondmultiple input gate circuits for respectively applying plural inputsignals and at least one clock signal to the input of said masterflip-flop, each of said input gate circuits including at least onemultiple emitter transistor and said input and clock signals have atleast two conditions; wherein e. said input signals are selectivelyapplied to said first and second multiple input gate circuits and saidclock signal is applied to said master flip-flop; and f. said masterflip-flop includes means responsive to one condition of said inputsignals and one condition of said clock signal for changing the state ofsaid master flip-flop, and said slave flip-flop includes meansresponsive to said master flip-flop and the other condition of saidclock signal for changing the state of said slave flip-flop after saidmaster flip-flop changes state.